1. Field of the Invention
The present invention relates generally to a method of manufacturing a semiconductor device and more particularly to a method of manufacturing an antireflection film used in photolithography.
2. Description of the Background Art
Hereinafter, the structure of a conventional semiconductor device will be described with reference to FIG. 31.
An active region 100 enclosed by an isolation oxide film 2 is formed on a semiconductor substrate 1.
A gate electrode 51 is formed in the active region 100 of the semiconductor substrate 1, with a gate oxide film 3 therebetween. Gate electrode 51 includes a first polycrystalline silicon film 4 and a first refractory metal silicide film 5.
Gate electrode 51 has its top portion covered with a silicon oxide film 6 and its side portion covered with a sidewall insulation film 7.
Impurity diffusion layers 8, 8 constituting source/drain regions are formed at the main surface of semiconductor substrate 1, with gate electrode 51 therebetween.
According to the above structure, an MOS type field effect transistor 50 is formed.
On one of the impurity diffusion layers 8, a first interconnection layer 52 including a second polycrystalline silicon layer 10 and a second refractory metal silicide layer 11 is formed.
On the other one of the impurity diffusion layers 8, a second interconnection layer 16 of aluminum layer is formed through a contact hole 15 provided in silicon oxide films 9 and 13 and a BPSG (Boro Phospho Silicate Glass) film 14.
A third interconnection layer 19 of aluminum is connected to second interconnection layer 16 through a contact hole 18 provided in a silicon oxide film 17.
Additionally, the entire surface of semiconductor substrate 1 is covered with a passivation film 20.
Manufacturing steps of the semiconductor device having the above structure will be described with reference to FIGS. 32-43
First, referring to FIG. 32, an oxide film 30 of SiO.sub.2 is formed to the thickness of 5 to 30 nm by the CVD method on semiconductor substrate 1. Thereafter, on oxide film 30, a polysilicon film 31 is formed to the thickness of 20 nm to 100 nm by the CVD method. Thereafter, on polysilicon film 31, a silicon nitride film 32 of Si.sub.3 N.sub.4 which is stoichiometrical silicon nitride, is formed to the thickness of 50 nm-400 nm.
Thereafter, referring to FIG. 33, a resist film 33 having a prescribed pattern is formed on silicon nitride film 32. Thereafter, silicon nitride film 32 and polysilicon film 31 are patterned using resist film 33 as a mask.
Then, referring to FIG. 34, resist film 33 is removed, and thereafter, a field oxide film 2 having the thickness of 200 nm to 600 nm is formed on the surface of semiconductor substrate 1 by thermal oxidation at a temperature in the range of from 600.degree. C. to 1300.degree. C.
Then, referring to FIG. 35, silicon nitride film 32, polysilicon film 31 and oxide film 30 are removed, and thereafter, a gate oxide film 3 having the thickness of 5 to 30 nm is formed on the surface of semiconductor substrate 1 by thermal oxidation.
Referring to FIG. 36, a first polycrystalline silicon film 4 doped with phosphorus or arsenic is formed to the thickness of 50-200 nm by vapor deposition method. A first refractory metal silicide layer 5 of tungsten silicide or the like is formed to the thickness of 50-300 mm by sputtering or the like.
A silicon oxide film 6 is formed on first refractory metal silicide film 5 by using vapor deposition method. A resist film 21 having a prescribed pattern is formed on the silicon oxide film 6 by photolithography.
Referring to FIG. 37, silicon oxide film 6 is processed using resist film 21 as a mask by reactive ion-etching method (hereinafter, referred to as RIE method) using carbon tetrafluoride or the like.
Referring to FIG. 38, after removing resist film 21, first refractory metal silicide film 5 and first polycrystalline silicon film 4 are patterned using silicon oxide film 6 as a mask by RIE method using chlorine or the like.
Then impurity such as phosphorus or boron is introduced to the surface of semiconductor substrate 1 using first refractory metal silicide film 5 and first polycrystalline silicon film 4 as a mask by ion implantation method to form impurity diffusion layers 8, 8.
Thereafter, a silicon oxide film having the thickness of about 50 to about 200 nm is deposited on the entire surface of semiconductor substrate 1. Then, the silicon oxide film is etched by anisotropic etching so as to form, on sidewalls of the first refractory metal silicide film 5 and the first polycrystalline silicon film 4, a sidewall insulating film 7, as shown in FIG. 39.
Then, using sidewall insulation film 7 as a mask, additional impurity ions are implanted to the surface of semiconductor substrate 1 to complete impurity diffusion layers 8, 8.
A silicon oxide film 9 is deposited on the entire surface of semiconductor substrate 1 by vapor deposition method. Then, a contact hole 12 shown in FIG. 40 is formed above one of the impurity diffusion layers 8 of silicon oxide film 9 by photolithography and RIE method.
Referring to FIG. 41, a second polycrystalline silicon film 10 of 50-200 nm in thickness including phosphorus or arsenic is deposited on the entire surface of semiconductor substrate 1 by vapor deposition method. A second refractory metal silicide film 11 of tungsten silicide or the like is formed on second polycrystalline silicon film 10 by sputtering or the like.
Referring to FIG. 42, second polycrystalline silicon film 10 and second refractory metal silicide film 11 are patterned into a prescribed shape by using photolithography and RIE method.
Referring to FIG. 43, silicon oxide film 13 is deposited on the entire surface of semiconductor substrate 1 by vapor deposition method. Then a BPSG film 14 is deposited on the silicon oxide film 13 by vapor deposition method. Then BPSG film 14 is heated at the temperature of approximately 850.degree. C. to complete an interlayer insulation film 14 having a relatively flat surface as shown in FIG. 43.
Referring to FIG. 44, a contact hole 15 reaching the other one of the impurity diffusion layers 8 is formed by using photolithography and RIE method.
Referring to FIG. 45, a second interconnection layer 16 of aluminum-silicon alloy or the like is formed on the entire surface of semiconductor substrate 1 by sputtering.
Referring to FIG. 46, a silicon oxide film 17 is deposited on the entire surface of semiconductor substrate 1 by using plasma enhanced vapor deposition method or the like.
Referring to FIG. 47, a contact hole 18 reaching to second interconnection layer 16 is formed at a prescribed position of silicon oxide film 17 by using photolithography or the like. Then a third interconnection layer 19 of aluminum-silicon alloy or the like is deposited and formed into a prescribed shape by using photolithography or the like.
Then a passivation film 20 of silicon oxide or the like is formed on the entire surface of semiconductor substrate 1 by using plasma enhanced vapor deposition method and the semiconductor device shown in FIG. 31 is completed.
In the semiconductor device having the above structure, it is necessary to arrange thinner wirings in higher density to improve the degree of integration.
Thus, to improve the degree of integration and to attain high density by using thinner wirings, it is necessary to carry out exposure with a light of shorter wavelength in photolithography. Recently, i-line having wavelength of 365 nm, KrF excimer laser having wavelength of 248 nm or the like is used as a light source.
However, when the wavelength of the exposure light is shortened as in the case of i-line or krF excimer laser beam, the reflectance of the interface between the silicon film or the refractory metal silicide film, and the resist film increases, causing a deformation of the resist pattern by the exposure light reflected transversely in the stepped portion of refractory metal silicide layer 5 having high reflectance as shown in FIG. 48, for example. To avoid this, the reflectance of the exposure light at the surface of the lower layer of the resist film is desired to be approximately 30% or less.
According to the structure shown in FIG. 48, the resist film is influenced by multi-reflection of exposure light in a transparent silicon oxide film 6. As a result, the reflectance at the interface between the resist film and the silicon oxide film 6 changes in the stepped portion or the like, preventing the patterning of the resist film to a desired shape.
Referring to FIG. 49, the relation between the thickness of the silicon oxide film provided on a tungsten silicide film and the reflectance at the interface between the silicon oxide film and the resist film, with the wavelength of the exposure light being 248 nm will be described, for example.
The absolute value of the reflectance of the silicon oxide film is, independent of its thickness, 35% or more and the reflectance varies up to approximately 50% according to the change in thickness of the silicon oxide film.
Thus, the thickness of the silicon oxide film changes in the stepped portion, and hence reflectance of the exposure light at the interface between the silicon oxide and the resist film changes, causing variation of pattern dimension of the resist film.
To avoid this, method of providing an anti-reflection film on the top surface of the resist film or between the resist film and a layer to be etched is known.
As described in Solid State Technology in Japanese, Jan. 1992 pp. 17, for example, there is a method of providing, as an anti-reflection film, titanium nitride, polymer or the like under a photoresist.
The anti-reflection film using such material has good optical characteristics, good shading and effectively reduces the reflection of exposure light. As a result, desired shape of the resist pattern can be obtained.
However, when titanium nitride or polymer is used as the above anti-reflection film, the following problems occur.
At first, a titanium compound such as titanium nitride is generally turned into vapor with low pressure. Therefore, it is difficult to obtain the titanium compound which has the same shape as the resist pattern by RIE method.
When an organic material such as polymer is used as an anti-reflection film, the material has the same characteristics as the resist film, and therefore it causes deformation of pattern of resist film during etching of the anti-reflection film.
The material such as the titanium compound or polymer described above sometimes has characteristics in etching different from the layer to be etched which is formed thereunder. Therefore, it is necessary to use a different etching apparatus than that for the layer to be etched in order to process the anti-reflection film.
Thus, the material of the conventional anti-reflection film causes increase of the number of steps for manufacturing semiconductor device, thereby increasing the cost of the semiconductor device.
Additionally, since it is difficult to process the anti-reflection film accurately, it is practically impossible to use an exposure light having a short wavelength in photolithography using the conventional anti-reflection film.
As a result, there is a limit in the high integration of a semiconductor device, causing difficulty in providing a semiconductor device with high integration at low price.
In the process for manufacturing the semiconductor device described above, the following problem has been encountered in the step of forming field oxide film 2 (FIGS. 32 to 34).
First, referring to FIG. 50, a gate electrode 51 of a MOS field effect transistor 50 is formed at a prescribed position of an active region 100 surrounded by an isolating oxide film 2. Generally, the width L of gate electrode 51 is referred to as the channel length (L), while the length of gate electrode 51 which corresponds to the width of the active region W is referred to as the channel width (W). The channel length (L) and channel width (W) are important factors defining the performance of MOS field effect transistor 50, and generally, it is desired that a plurality of MOS field effect transistors formed on the same semiconductor well all have the same channel length (L) and channel width (W) so that all the MOS field effect transistors have the same performance.
However, channel width (W) depends on the width (W) of active region 100, and the width (W) of active region 100 depends on the precision in manufacturing the field oxide film 2. Accordingly, performance of the MOS field effect transistors may be made uniform, if field oxide film 2 is formed with high precision.
However, the dimensional precision of the field oxide film 2 cannot be improved from the following reasons.
In the step of forming the field oxide film shown in FIGS. 32 to 34, there is provided a silicon nitride film 32 of Si.sub.3 N.sub.4, which is a stoichiometrical silicon nitride formed by thermal CVD, which is an optically transparent film. Therefore, in the step of patterning the resist film by lithography shown in FIG. 33, there is generated multiple reflection of the exposure light in silicon nitride film 32. As a result, the energy of exposure light with which resist film 33 is irradiated changes dependent on the change of thickness of nitride film 33, so that desired pattern of resist film 33 cannot be formed.
For example, if the thickness of oxide film 30 is fixed at 15 nm, the thickness of polysilicon film 31 is fixed at 50 nm and the thickness of resist film 33 is fixed at 1000 nm and the thickness of silicon nitride film 32 is changed from 160 nm to 240 nm, the reflectance of exposure light at the surface of resist film 33 changes from 2% to 23%, as shown in FIG. 51. As a result, the energy of exposure light with which resist film 33 is irradiated is changed.
Further, when the thickness of the resist film 33 is changed from 700 nm to 800 nm under the same conditions as mentioned above, the reflectance of the exposure light at the interface between resist film 33 and the silicon nitride film varies as wide as from 2% to 36% as shown in FIG. 52, because of multiple reflection in the resist film. At this time, the thickness of the resist film formed on the semiconductor wafer on which a plurality if semiconductor devices are to be formed, which is desired to be uniform ideally, comes to have the error of about .+-.100 nm actually. As a result, the energy of the exposure light with which the resist film 33 is irradiated differs from portion to portion in the semiconductor wafer.